1. Field of the Invention
This invention relates generally to digital logic design and testability of semiconductor chips and, more particularly, to a method to improve random pattern testability (RPT) analysis of a hierarchical design of a semiconductor chip.
2. Discussion of the Related Art
Random pattern testability of semiconductor chips has become increasingly important due to the emphasis on chip built-in self-test methods (BIST). BIST is a way of testing chip logic without the use of an external tester as disclosed in P. H. Bardell and W. H. McAnney, xe2x80x9cSelf-Testing of Multichip Modules,xe2x80x9d Proceedings of the IEEE International Test Conference, 1982, pp. 200-204, which is hereby incorporated by reference. Once a chip is manufactured, it is subjected to electronic testing to verify that it works properly. BIST is increasingly an important part of this testing since less complex testers are required and perhaps no tester is required. After the semiconductor chip is assembled in a more complex system (a multi-chip circuit board, for example), BIST is often automatically run whenever the chip is first turned on. It may also be run during diagnostic or trouble-shooting routines. In many cases, BIST is the only test that may be run on a chip once it is installed in a more complex system like a multi-chip circuit board. The quality of the circuit board test is, therefore, heavily dependent on the quality of the BIST test, since there may be many semiconductor chips on the circuit board itself, each testable only by BIST at the assembly level.
Most BIST techniques use a pseudo-random pattern generator (PRPG) to generate test patterns. The PRPG is an internal logic circuit in the semiconductor chip itself that generates a random, but repeatable set of 1s and 0s that are applied to chip inputs and latches. E. B. Eichelberger, E. Lindbloom, J. A. Waicukauski, T. W. Williams, xe2x80x9cStructured Logic Testingxe2x80x9d, pp. 90-103, Prentice Hall, 1991. An exemplary way of applying PRPG data to latches is through a scan chain. E. B. Eichelberger and T. W. Williams, xe2x80x9cA Logic Design Structure For LSI Testability,xe2x80x9d Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 462-468 describes such a scan technique, which is hereby incorporated by reference. In its most common implementation, the probability of a 1 at a latch or input equals the probability of a 0 =0.5 (i.e., P(0)=P(1)=0.5).
In general, it is not possible to test all logic on a semiconductor chip using BIST. One of the most common reasons for this is that certain logic structures are generally random pattern resistant. For example, the 32-input AND circuit 10, shown in FIG. 1, is random pattern resistant. The 32-input AND circuit 10 includes a first 16-input AND circuit 12 and a second 16-input AND circuit 14 each fed to a separate AND gate 16. Each AND circuit 12 and 14 also include a plurality of individual AND gates 18. All AND inputs 20 are assumed to be controllable (fed directly by latches), and the output 22 of AND gate 16 is assumed to be the only observable point (directly feeds a latch). In order to test for single stuck-at faults on any one of the blocks in the first level, the 32-inputs 20 have to be specified with 31-inputs 20 at xe2x80x9c1xe2x80x9d to propagate a potential fault to the observable point or output 22. In other words, should 31 inputs 20 be forced to a xe2x80x9c1xe2x80x9d and one input 20 be forced to a xe2x80x9c0xe2x80x9d if the circuit 10 is operating correctly, a xe2x80x9c0xe2x80x9d should be observed at the output 22. If the circuit 10 is not operating properly, a fault or a xe2x80x9c1xe2x80x9d would be observed at the output 22.
The probability of 31-inputs 20 being a xe2x80x9c1xe2x80x9d and one of the inputs 20 being a xe2x80x9c0xe2x80x9d randomly occurring in any single pattern is xc2xd32. This probability is basically 0 for any practical test time. Methods exist that analyze logic for random pattern testability (RPT) and suggest test points that can improve the RPT. These methods are discussed in Sunil K. Jain and Vishwani D. Agrawal (AT and T Bell Laboratories), xe2x80x9cStatistical Fault Analysis,xe2x80x9d IEEE Design and Test of Computers, Vol 2, No. 2, February 1985, pp. 38-44; S. K. Jain and Vishwani D. Agrawal, xe2x80x9cSTAFAN: An Alternative To Fault Simulation,xe2x80x9d ACM/IEEE 21st Design Automation Conference Proceedings, June 1984, pp. 18-23; and U.S. Pat. No. 3,761,695, each of which are hereby incorporated by reference.
A more testable version of the 32-input AND circuit 10xe2x80x2, is shown in FIG. 2. In this regard, like reference numerals will be used to identify like structures with respect to the 32-input AND circuit 10, shown in FIG. 1. As shown in FIG. 2, four test points 24, using observation latches 26 (i.e., two in each 16-input AND circuits 12 and 14) have been added to the design. Each observation latch 26 is based upon level sensitive scan design (LSSD) and includes a pair of master-slave latches which enables and provides observable and controllable points 24. LSSD is further disclosed in detail in E. B. Eichelberger and T. W. Williams, xe2x80x9cA Logic Design Structure for LSI Testability,xe2x80x9d Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 462-468, which is hereby incorporated by reference.
In order to test the test points 24, now only 8-inputs 20 must be specified. The one under test (i.e., xe2x80x9c0xe2x80x9d) and the next 7-inputs 20 set to a xe2x80x9c1xe2x80x9d. The probability of this result randomly occurring in any single pattern is xc2xd8. This is only {fraction (1/256)}. Since generally tens of thousands of patterns are applied, this is now easily testable. In fact, with this configuration, all but three AND gates are testable. In this regard, the last AND gates 18 in circuits 12 and 14 and the AND gate 16 are not testable. Therefore, the circuits in these last two stages may still have some faults (input stuck at 0, for example), which are not testable as shown in FIG. 2.
In order to test these last two stages, additional test points, generally known as control test points, must be added to the circuit 10xe2x80x2. These additional test points are shown in FIG. 3. Here again, like reference numerals will be used to identify like structures with respect to the circuit 10xe2x80x3. As shown in FIG. 3, two control latches 28 are added to each circuit 12 and 14 which again comprise a pair of master and slave latches. A pair of two way OR gates 30 are also added to each circuit 12 and 14. The addition of the control latches 28 and the OR gates 30 enables an alternate way to set an input/output to a xe2x80x9c1xe2x80x9d state. In this regard, in order to test the final AND gate 16 for a stuck-at-0 fault on either input, both inputs must be set to a xe2x80x9c1xe2x80x9d.
In the 32-way AND circuits 10 and 10xe2x80x2, shown in FIGS. 1 and 2, the 32-inputs 20 have to be set to xe2x80x9c1xe2x80x9d. This is not possible with random patterns. In the 32-way AND circuit 10xe2x80x3 of FIG. 3, the states of only four control latches 28 need to be specified, which is easily tested with random patterns. In other words, upon setting the control latches 28 to a xe2x80x9c1xe2x80x9d state, each two-way OR 30 will be forced to have a xe2x80x9c1xe2x80x9d output, thereby causing the last AND gates 18 in circuits 12 and 14 to provide xe2x80x9c1xe2x80x9d inputs to the AND gate 16 to confirm the operation of the entire circuit 10xe2x80x3. This modified 32-input AND circuit 10xe2x80x3 is one hundred percent (100%) random pattern testable based upon the addition of the observation latches 26, the control latches 28 and the OR gates 30. However, one disadvantage with this circuit 10xe2x80x3 is that the OR gates 30 are placed in-line with each circuit 12 and 14, thus causing these circuits 12 and 14 to run slower than if the OR gates 30 were not present.
A flow chart illustrating a typical prior art random pattern testability analysis or process 32 is shown in FIG. 4. The RPT analysis 32 receives an input from a design netlist input block 34. The design netlist block 34 identifies the circuit or entity being analyzed and is assumed to have all netlist inputs directly controllable and all netlist outputs directly observable. The design netlist block 34 provides a logical description of the design of the chip by mapping all of the inter-connections throughout the chip. The other input to the RPT analysis 32 is a maximum pattern count block 36. The maximum pattern count block 36 identifies the number of random patterns to run in the RPT analysis 32 which can range from several thousand to several million random patterns. The number of random patterns used is generally only governed by the test time and the test cost. The more random patterns run, the higher the test time and the higher the test cost. The input blocks 34 and 36 are directed to a random pattern simulation block 38. The random pattern simulation block 38 assumes fixed probabilities for all inputs P(0). In this regard, the input probability of a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d at each input is generally set to 0.5. However, this probability input may be adjusted to be, for example, thirty percent (30%) for a xe2x80x9c1xe2x80x9d and seventy percent (70%) for a xe2x80x9c0xe2x80x9d, or any other appropriate values.
From the random pattern simulation block 38, the RPT analysis 32 progresses to the RPT algorithm block 40. The RPT algorithm 40 is a known prior art algorithm and is further disclosed in detail in references to Sunil K. Jain and Vishwani D. Agrawal (AT and T Bell Laboratories), xe2x80x9cStatistical Fault Analysisxe2x80x9d, IEEE Design and Test of Computers, Vol 2 No. 2, February 1985, pp. 38-44; S. K. Jain and Vishwani D. Agrawal, xe2x80x9cSTAFAN: an Alternative to Fault Simulation,xe2x80x9d ACM/IEEE 21st Design Automation Conference Proceedings, June 1984, pp.18-23; and U.S. Pat. No. 3,761,695, which are each hereby incorporated by reference. The output from the RPT algorithm 40 is an RPT percent coverage block 42, an identification of test points to improve RPT block 44 and a signal probabilities block 46. The RPT percent coverage block 42 identifies the percent of the circuit or chip that is random pattern testable. The test points block 44 are identified as control and observation points and are suggested conditions to the logic circuit to improve the RPT percent coverage 42. In other words, the test points block 44 identifies the additional observation latches, control latches, OR gates, etc. that may be added to the circuit, such as that shown in FIGS. 1-3 to improve the RPT percent coverage 44. The logic designer may or may not add these particular circuits to the logic depending on how close the design is to the testability target, scheduling, available circuit area, etc. The signal probabilities block 46 identifies the signal probabilities for each input and output of each gate or logic in the circuit tested. This information is generally provided but not used in the design or test process.
The above RPT analysis 32 works well for small chips where all logic or gates elements are analyzed at once. However, chips are rapidly becoming larger, with tens of millions of transistors becoming commonplace. Because of this, logic design is now generally performed in a hierarchical fashion. Smaller logical partitions of a chip, referred to as xe2x80x9cmacrosxe2x80x9d are designed first, and they are stitched together later. One semiconductor chip may have dozens to hundreds of macros. RPT analysis 32 cannot practically be done on an entire semiconductor chip for several reasons. These reasons include that the full chip model is too large, the simulation run times are very long, the full chip model is not ready until late in the design cycle which is generally too late to make any changes, and errors or problems in a single macro can cause the entire simulation to run to abort.
What is needed then is a method to improve random pattern testability analysis of a hierarchical design which does not suffer from these disadvantages. This will, in turn, provide a more robust testing method that enables testing earlier in the design sequence, enables changing of the logic circuitry earlier in the design sequence, enables testing of substantially large semiconductor chips and provides a more reliable RPT analysis. It is, therefore, an object of the present invention to provide such a method to improve random pattern testability analysis of a hierarchical design.
This invention is a technique to more accurately evaluate random pattern testability (RPT) of a hierarchical chip design. Use of this technique will improve the accuracy of RPT at lower levels of the hierarchy (such as logic macros) prior to combining them together into a complete chip. The resultant macro testability reports and test point insertion information will be more accurate. More effective RPT fixes will be done at macro level. As a result, there will be fewer random pattern testability problems visible once the entire chip is assembled from the lower hierarchy levels and simulated. Fewer iterations at a chip level will be required to meet RPT targets.
Iterations at a macro level use much less space (memory) and time (CPU) than iterations at a chip level by a factor of 10 to 100 or more. Macros are designed much sooner than the full chip model. There is more time for logic and circuit layout changes to fix test problems. Macro simulation models are much less prone to unexpected problems compared to the full chip model. A problem with one macro (out of hundreds) can cause a problem with the chip model and finally, this new method does not require the design to be complete. As each macro in the design is done, the RPT calculations become more accurate.
In one preferred embodiment, a method to improve random pattern testability (RPT) of a hierarchical semiconductor chip design formed from a plurality of macros, with each macro identifying a particular portion of the semiconductor chip design is provided. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying the logical description of a second portion of a semiconductor chip design and performing RPT analysis on the second macro netlist. The first macro netlist and the second macro netlist are combined and RPT analysis is performed on the combination of the first and second macro netlists.
Use of the present invention provides a method to improve random pattern testability analysis of a hierarchical semiconductor chip design. As a result, the aforementioned disadvantages associated with the current testing procedures for semiconductor chips have been substantially reduced or eliminated.